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IS42S16800A1
8Meg x16 128-MBIT SYNCHRONOUS DRAM
ISSI
(R)
PRELIMINARY INFORMATION MAY 2006
FEATURES
* Clock frequency: 143 MHz * Fully synchronous; all signals referenced to a positive clock edge * Internal bank for hiding row access/precharge * Power supply VDD IS42S16800A1 * LVTTL interface * Programmable burst length - (1, 2, 4, 8, full page) * Programmable burst sequence: Sequential/Interleave * Auto Refresh (CBR) * Self Refresh with programmable refresh periods * 4096 refresh cycles every 64 ms * Random column address every clock cycle * Programmable CAS latency (2, 3 clocks) * Burst read/write and burst read/single write operations capability * Burst termination by burst stop and precharge command * Lead-free Availability VDDQ
OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows.
IS42S16800A1 2M x16x4 Banks 54-pin TSOPII
3.3V 3.3V
KEY TIMING PARAMETERS
Parameter CK Cycle Time CAS Latency = 3 CAS Latency = 2 CK Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -7 7 7.5 143 133 5 5.4 Unit ns ns Mhz Mhz ns ns
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 05/01/06
1
IS42S16800A1
DEVICE OVERVIEW
The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V VDD and 3.3V VDDQ memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 512 columns by 16 bits. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.
ISSI
(R)
A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option.
FUNCTIONAL BLOCK DIAGRAM (2MX16X4 BANKS)
CK CKE CS RAS CAS WE
UDQM LDQM COMMAND DECODER & CLOCK GENERATOR
DATA IN BUFFER
16 16 2
MODE REGISTER
12
REFRESH CONTROLLER
DQ 0-15
SELF REFRESH CONTROLLER
A10
A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1
12
DATA OUT BUFFER
16 16
VDD/VDDQ Vss/VssQ
REFRESH COUNTER
4096 4096 4096 4096
ROW DECODER
MULTIPLEXER
MEMORY CELL ARRAY
12
ROW ADDRESS LATCH
12
ROW ADDRESS BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN ADDRESS LATCH
9
512 (x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN ADDRESS BUFFER
9
2
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Rev. 00B 05/01/06
IS42S16800A1
PIN CONFIGURATIONS
54 pin TSOP - Type II for x16
ISSI
(R)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
PIN DESCRIPTIONS
A0-A11 A0-A8 BA0, BA1 DQ0 to DQ15 CK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE LDQM UDQM VDD Vss VDDQ VssQ NC Write Enable x16 Lower Byte, Input/Output Mask x16 Upper Byte, Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection
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IS42S16800A1
PIN FUNCTIONS
Symbol A0-A11 Type Input Pin Function (In Detail)
ISSI
(R)
Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (column address A0-A8 (x16); with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" for details on device commands. The CKE input determines whether the CK input is enabled. The next rising edge of the CK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode. CKE is an asynchronous input. CK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. Data on the Data Bus is latched on DQ pins during Write commands, and buffered for output after Read commands. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. VDDQ is the output buffer power supply. VDD is the device internal power supply. VSSQ is the output buffer ground. VSS is the device internal ground.
BA0, BA1 CAS CKE
Input Pin Input Pin Input Pin
CK CS
Input Pin Input Pin
LDQM, UDQM
Input Pin
DQ0-DQ7 or DQ0-DQ15 RAS WE VDDQ VDD VSSQ VSS
Input/Output Input Pin Input Pin Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin
4
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IS42S16800A1
Power On and Initialization
ISSI
(R)
The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CK signal must be started at the same time. After power on, an initial pause of 200s is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
Programming the Mode Register
For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set Command is issued. After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. CAS Latency The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section.
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N
5
IS42S16800A1
ISSI
Address Bus (Ax)
(R)
Mode Register Operation (Address Input For Mode Set)
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Operation Mode
CAS Latency
BT
Burst Length
Mode Register(Mx)
Burst Type
M3 0 1 Type Sequential Interleave
Operation Mode
M14 M13 M12 M11 M10 M9 0 0 0 0 0 0 0 0 0 0 0 1 M8 0 0 M7 0 0 Mode Normal Multiple Burst with Single Write
Burst Length
M2 0 0 0 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Length Sequential Interleave 1 2 4 8 1 2 4 8
CAS Latency
M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
0 1 1 1 1
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
6
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IS42S16800A1
Burst Mode Operation
ISSI
(R)
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A11, BA0, and BA1. The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 and full page sequential burst. Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected.
Burst Length and Sequence
Burst Length 2 Starting Address (A2 A1 A0) xx0 xx1 x00 4 x01 x10 x11 000 001 010 8 011 100 101 110 111 256 (Full Page) n= A0-A7 Sequential Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Cn, Cn1+2, Cn+3, C+4, ... Interleave Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Not supported
Note: Page length is a function of I/O organization and column addressing. x16 organization (CA0-CA8); Page Length = 512 bits
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7
IS42S16800A1
Bank Activate Command
ISSI
(R)
In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select address BA0 - BA1 is used to select the desired bank. The row address A0 - A11 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max).
Bank Activate Command Cycle
(CAS Latency = 3, tRCD = 3)
CK T0 T1 T2 T3
..........
Tn
Tn+1
Tn+2
Tn+3
ADDRESS
Bank A Row Addr. RAS-CAS delay (tRCD)
Bank A Col. Addr.
..........
Bank B Row Addr.
Bank A Row Addr.
RAS - RAS delay time (tRRD) Write A with Auto Precharge .......... Bank B Activate NOP Bank A Activate NOP
COMMAND
: "H" or "L"
Bank A Activate
NOP
NOP
RAS Cycle time (tRC)
Bank Select
The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation.
Bank Selection Bits
BA0 0 1 0 1 BA1 0 0 1 1 Bank Bank 0 Bank 1 Bank 2 Bank 3
8
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IS42S16800A1
Read and Write Access Modes
ISSI
(R)
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low at the clock's rising edge after the necessary RAS to CAS delay (tRCD). WE must also be defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address. The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles up to 133 MHz for PC133 or upto 166MHz for PC166 devices. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register. Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the new address. Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock cycle.
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IS42S16800A1
Burst Read Command
ISSI
(R)
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register.
Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
tCK3, DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears.
Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tCK3, DQs
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
10
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IS42S16800A1
Read Interrupted by a Write
ISSI
(R)
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus.
Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
CK T0 T1 T2 T3 T4 T5 T6 T7 T8
DQM
DQM high for CAS latency = 2 only. Required to mask first bit of READ data.
COMMAND
NOP
READ A
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
DIN A0
DIN A1
DIN A2
DIN A3
tCK3, DQs
: "H" or "L"
DIN A0
DIN A1
DIN A2
DIN A3
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IS42S16800A1
ISSI
(Burst Length = 4, CAS latency = 2, 3) T1 T2 T3 T4 T5 T6 T7 T8
(R)
Non-Minimum Read to Write Interval
CK
T0
DQM
COMMAND
READ A
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
CL = 2: DQM needed to mask first, second bit of READ data.
CAS latency = 2
tCK2, DQs
DIN A0
DIN A1
DIN A2
DIN A3
CL = 3: DQM needed to mask first bit of READ data.
CAS latency = 3
tCK3, DQs
DIN A0
DIN A1
DIN A2
DIN A3
: DQM high for CAS latency = 2 : DQM high for CAS latency = 3
12
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IS42S16800A1
Burst Write Command
ISSI
(R)
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored.
Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQs
: "H" or "L"
DIN A0
DIN A1
DIN A2
DIN A3
The first data element and the Write are registered on the same clock edge.
Extra data is masked.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
1 CK Interval
DQs
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
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IS42S16800A1
Write Interrupted by a Read
ISSI
(R)
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory.
Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tCK2, DQs
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
CAS latency = 3
tCK3, DQs
DIN A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
: "H" or "L"
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention.
14
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IS42S16800A1
Non-Minimum Write to Read Interval
ISSI
(Burst Length = 4, CAS latency = 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
(R)
CK
T0
COMMAND
WRITE A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
tCK2, DQs
DIN A0
DIN A1
DOUT B0
DOUT B1
DOUT B2
DOUT B3
CAS latency = 3
tCK3, DQs
DIN A0
DIN A1
DOUT B0
DOUT B1
DOUT B2
DOUT B3
: "H" or "L"
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention.
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IS42S16800A1
Auto-Precharge Operation
ISSI
(R)
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can also be implemented during Write commands. A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended.
Burst Read with Auto-Precharge
(Burst Length = 1, CAS Latency = 2, 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
CAS latency = 2
Auto-Precharge
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tRP
DOUT A0
tCK2, DQs
CAS latency = 3
*
tRP
DOUT A0
tCK3, DQs
Begin Auto-precharge
*
tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
*Bank can be reactivated at completion of t
RP.
16
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Rev. 00B 05/01/06
IS42S16800A1
Burst Read with Auto-Precharge
ISSI
(Burst Length = 2, CAS Latency = 2, 3)
T1 T2 T3 T4 T5 T6 T7 T8
(R)
CK
T0
COMMAND
CAS latency = 2
Auto-Precharge
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tRP
DOUT A0 DOUT A1
tCK2, DQs
CAS latency = 3
*
tRP
tCK3, DQs
Begin Auto-precharge
*
DOUT A1
DOUT A0
*
Bank can be reactivated at completion of tRP. tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Burst Read with Auto-Precharge
(Burst Length = 4, CAS Latency = 2, 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK
COMMAND
CAS latency = 2
Auto-Precharge
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tRP
DOUT A0 DOUT A1 DOUT A2 DOUT A3
tCK2, DQs
CAS latency = 3
*
tRP
tCK3, DQs
*
DOUT A3
RP.
DOUT A0
DOUT A1
DOUT A2
Begin Auto-precharge
tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
*Bank can be reactivated at completion of t
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IS42S16800A1
ISSI
(R)
Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP.
Burst Read with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 2, 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
CAS latency = 2
Auto-Precharge
READ A
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
tRP
DOUT A0 DOUT A1
tCK2, DQs
CAS latency = 3
*
DOUT B0 DOUT B1 DOUT B2 DOUT B3
tRP
DOUT A0 DOUT A1
tCK3, DQs
*
DOUT B0 DOUT B1 DOUT B2 DOUT B3
RP RP
be reactivated t. *Bankiscanfunction of clockat completion ofspeed sort. t a cycle time and See the Clock Frequency and Latency table.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.
Burst Read with Auto-Precharge Interrupted by Write
(Burst Length = 8, CAS Latency = 2) CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
CAS latency = 2
Auto-Precharge
READ A
NOP
NOP
NOP
WRITE B
NOP
NOP
NOP
NOP
tRP
DOUT A0 DIN B0 DIN B1
tCK2, DQs
*
DIN B2 DIN B3 DIN B4
DQM
be reactivated t. *Bankiscanfunction of clockat completion ofspeed sort.. t a cycle time and
RP RP
See the Clock Frequency and Latency table.
18
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Rev. 00B 05/01/06
IS42S16800A1
ISSI
(R)
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing autoprecharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied.
Burst Write with Auto-Precharge
CK
T0
T1
T2
T3
T4
(Burst Length = 2, CAS Latency = 2, 3) T5 T6 T7 T8
COMMAND
CAS latency = 2
Auto-Precharge
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDAL
DIN A0 DIN A1
tCK2, DQs
CAS latency = 3
*
tDAL
tCK3, DQs
*
can be reactivated completion of t . *Bankis a function of clockatcycle time and speed sort. t
DAL DAL
DIN A0
DIN A1
See the Clock Frequency and Latency table.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the write. The bank undergoing auto-precharge can not be reactivated until tDAL is satisfied.
Burst Write with Auto-Precharge Interrupted by Write
(Burst Length = 4, CAS Latency = 3) T6 T7 T8
T0 CK
T1
T2
T3
T4
T5
COMMAND
CAS latency = 3
Auto-Precharge
WRITE A
NOP
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
tDAL
DIN A0 DIN A1 DIN B0 DIN B1 DIN B2
tCK3, DQs
*
DIN B3
be reactivated completion of t . *Bankiscanfunction of clockatcycle time and speed sort. t a
DAL DAL
See the Clock Frequency and Latency table.
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19
IS42S16800A1
ISSI
T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 3) T6 T7 T8
(R)
Burst Write with Auto-Precharge Interrupted by Read
CK
T0
COMMAND
CAS latency = 3
Auto-Precharge
WRITE A
NOP
NOP
READ B
NOP
NOP
NOP
NOP
NOP
tDAL
DIN A0 DIN A1 DIN A2 DOUT B0
*
DOUT B1 DOUT B2
tCK3, DQs
tDAL is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
* Bank A can be reactivated at completion of tDAL.
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which bank(s) is to be precharged when the command is issued.
Bank Selection for Precharge by Address Bits
A10 LOW HIGH Bank Select BA0, BA1 DON'T CARE Precharged Bank(s) Single bank defined by BA0, BA1 All Banks
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as tDPL, Data-in to Precharge delay. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP).
20
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IS42S16800A1
Burst Read Followed by the Precharge Command
ISSI
(Burst Length = 4, CAS Latency = 3) T1 T2 T3 T4 T5 T6 T7 T8
(R)
CK
T0
COMMAND
READ Ax0
NOP
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
tRP
CAS latency = 3
*
tCK2, DQs
DOUT Ax0
DOUT Ax1
DOUT Ax2
DOUT Ax3
*
Burst Write Followed by the Precharge Command
Bank A can be reactivated at completion of tRP. tRP is a function of clock cycle and speed sort.
(Burst Length = 2, CAS Latency = 2) CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
Activate Bank Ax
NOP
WRITE Ax0
NOP
NOP
Precharge A
NOP
NOP
tDPL
tRP
*
RP
CAS latency = 2
tCK2, DQs
DIN Ax0
DIN Ax1
can reactivated at completion of t * Bankand t be are functions of clock cycle and .speed sort. t
DPL RP
See the Clock Frequency and Latency table.
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21
IS42S16800A1
Precharge Termination
ISSI
(R)
The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge
(Burst Length = 8, CAS Latency = 2, 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
READ Ax0
NOP
NOP
NOP
Precharge A
NOP
NOP
NOP
NOP
tRP
CAS latency = 2 DOUT Ax0 DOUT Ax1 DOUT Ax2 DOUT Ax3
*
tRP
tCK2, DQs
CAS latency = 3
*
DOUT Ax3
tCK3, DQs
DOUT Ax0
DOUT Ax1
DOUT Ax2
*
Bank A can be reactivated at completion of tRP. tRP is a function of clock cycle time and speed sort. See the Clock Frequency and Latency table.
22
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Rev. 00B 05/01/06
IS42S16800A1
ISSI
(R)
Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, tDPL.
Precharge Termination of a Burst Write
(Burst Length = 8, CAS Latency = 2, 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8
COMMAND
NOP
NOP
WRITE Ax0
NOP
NOP
NOP
Precharge A
NOP
NOP
DQM
tDPL
CAS latency = 2
tCK2, DQs
DIN Ax0
DIN Ax1
DIN Ax2
CAS latency = 3
tDPL
DIN Ax0 DIN Ax1 DIN Ax2
tCK3, DQs
tDPL is an asynchronous timing and may be completed in one or two clock cycles
depending on clock cycle time.
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IS42S16800A1
Automatic Refresh Command (CAS before RAS Refresh)
ISSI
(R)
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the RAS cycle time (tRC).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus the Self Refresh exit time (tSREX).
24
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Rev. 00B 05/01/06
IS42S16800A1
Power Down Mode
ISSI
(R)
In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect Command) is required on the next rising clock edge.
Power Down Mode Exit Timing
Tm CK
tCK
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+ 8
CKE
tCES(min)
COMMAND
: "H" or "L"
NOP
COMMAND
NOP
NOP
NOP
NOP
NOP
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25
IS42S16800A1
Data Mask
ISSI
(R)
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of CAS latency.
Data Mask Activated during a Read Cycle
(Burst Length = 4, CAS Latency = 2)
CK T0 T1 T2 T3 T4 T5 T6 T7 T8
DQM
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQs
: "H" or "L"
DOUT A0
DOUT A1
A two-clock delay before the DQs become Hi-Z
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares.
26
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IS42S16800A1
Clock Suspend Mode
ISSI
(R)
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or "freezes" any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and the time at which the SDRAM's operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited.
Clock Suspend during a Read Cycle
(Burst Length = 4, CAS Latency = 2) T6 T7 T8
CK CKE
T0
T1
T2
T3
T4
T5
A one clock delay to exit the Suspend command A one clock delay before suspend operation starts
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
DQs
: "H" or "L"
DOUT A0
DOUT A1
DOUT A2
DOUT element at the DQs when the suspend operation starts is held valid
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Suspend mode is exited.
Clock Suspend during a Write Cycle
(Burst Length = 4, CAS Latency = 2)
CK T0 T1 T2 T3 T4 T5 T6 T7 T8
CKE
A one clock delay before suspend operation starts
A one clock delay to exit the Suspend command
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
DQs
: "H" or "L"
DIN A0
DIN A1
DIN A2
DIN A3
DIN is masked during the Clock Suspend Period
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IS42S16800A1
ISSI
CKE Device State Idle Idle Idle Idle (SelfRefresh) See Current State Table See Current State Table Idle Active Active Active Active Any Any Active Active Active Active Idle/Active Any (Power Down) Previous Cycle H H H L H H H H H H H H H H H L H H H L Current Cycle X H L H X X X X X X X X X X L H X X L H CS L L L H L L L L L L L L L L H X X X X H L H L RAS L L L X H L L L H H H H H H X X X X X X H X H CAS L L L X H H H H L L L L H H X X X X X X H X H WE L H H X H L L H L L H H L H X X X X X X H X H DQM X X X X X X X X X X X X X X X X L H X X X X X BS X BS BS BS BS BS X X X X X X X X X BA0, BA1 A10 OP Code X X X L H X X X X X 2 2 2 2 2 2 A11, A9-A0
(R)
Command Truth Table (See note 1)
Function Mode Register Set Auto (CBR) Refresh Entry Self Refresh Exit Self Refresh Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto-Precharge Read Read with Auto-Precharge Reserved No Operation Device Deselect Clock Suspend Mode Entry Clock Suspend Mode Exit Data Write/Output Enable Data Mask/Output Disable Power Down Mode Entry Power Down Mode Exit Notes
Row Address L H L H X X X X X X X X X Column Column Column Column X X X X X X X X X
4 5 6, 7 6, 7
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the Current State Truth Table. 2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1 selects bank 3. 3. Not applicable. 4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can't remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. 7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
28
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IS42S16800A1
Clock Enable (CKE) Truth Table
CKE Current State Previous Cycle H L L Self Refresh L L L L H Power Down L L L H H H H H All Banks Idle H H H H H L H Any State other than listed above H L L Current Cycle X H H H H H L X H H L H H H H H L L L L L X H L H L CS X H L L L L X X H L X H L L L L H L L L L X X X X X RAS X X H H H L X X X X X X H L L L X H L L L X X X X X Command CAS X X H H L X X X X X X X X H L L X X H L L X X X X X WE X X H L X X X X X X X X X X H L X X X H L X X X X X X X Entry Self Refresh Mode Register Set Power Down X X CBR Refresh Mode Register Set BA0, BA1 X X X X X X X X X X X A11 - A0 X X X X X X X X X X X INVALID Action
ISSI
Notes 1 2 2 2 2 2
(R)
Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle ILLEGAL Maintain Power Down Mode
1 2 2
3 Refer to the Idle State section of the Current State Truth Table 3 3
OP Code
4 3
Refer to the Idle State section of the Current State Truth Table
3 3 4
OP Code X X X X X X X X X X
4
Refer to operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend 5
1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock after CKE goes high. 3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table.
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IS42S16800A1
ISSI
(Part 1 of 3)(See note 1)
Command Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Continue the Burst Continue the Burst 4 4 6 4 5 4 4 RAS CAS WE BA0,BA1 L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X X BS BS BS BS X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X A11 - A0 X X Column Column X X Description Mode Register Set Auto or Self Refresh Precharge Write w/o Precharge Read w/o Precharge No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect OP Code 2
(R)
Current State Truth Table
Current State CS L L L Idle L L L L H L L L Row Active L L L L H L L L Read L L L L H L L L Write L L L L H
Notes
2, 3
Row Address Bank Activate
Row Address Bank Activate
7, 8 7, 8
Row Address Bank Activate
8, 9 8, 9
Row Address Bank Activate
8, 9 8, 9
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
30
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Rev. 00B 05/01/06
IS42S16800A1
Current State Truth Table
Current State CS L L Read with Auto Precharge L L L L L H L L L Write with Auto Precharge L L L L H L L L L L L L H L L L Row Activating L L L L H
ISSI
(Part 2 of 3)(See note 1)
Command Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row Active after tRCD No Operation; Row Active after tRCD 4 4, 10 4 4 4 4 4 4 4 4 4 4 4 4 4 Notes A11 - A0 X X Column Column X X OP Code X BS BS BS BS X X OP Code X BS BS BS BS X X OP Code X BS BS BS BS X X X X Column Column X X X X X Column Column X X Description Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X X BS BS BS BS X X OP Code
(R)
RAS CAS WE BA0,BA1 L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X
Row Address Bank Activate
Row Address Bank Activate
Precharging
X Precharge Row Address Bank Activate Column Column X X Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect
Row Address Bank Activate
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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IS42S16800A1
Current State Truth Table
Current State CS L L L Write Recovering L L L L H L L Write Recovering with Auto Precharge L L L L L H L L L Refreshing L L L L H L L Mode Register Accessing L L L L L H
ISSI
(Part 3 of 3)(See note 1)
Command RAS CAS WE BA0,BA1 L L L L H H H X L L L L H H H X L L L L H H H X L L L L H H H X L L H H L L H X L L H H L L H X L L H H L L H X L L H H L L H X L H L H L H H X L H L H L H H X L H L H L H H X L H L H L H H X X BS BS BS BS X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X X BS BS BS BS X X OP Code X X Column Column X X A11 - A0 X X Column Column X X Description Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row Active after tDPL No Operation; Row Active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles 4 4 4 4 9 9 OP Code Action
(R)
Notes
Row Address Bank Activate
Row Address Bank Activate
4, 9 4, 9
Row Address Bank Activate
Row Address Bank Activate
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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IS42S16800A1
Absolute Maximum Ratings
Symbol VDD VDDQ VIN VOUT TA TSTG PD IOUT Parameter Power Supply Voltage Power Supply Voltage for Output Input Voltage Output Voltage Operating Temperature (ambient) Storage Temperature Power Dissipation Short Circuit Output Current Rating -1.0 to +4.6 -1.0 to +4.6 -0.3 to VDD+0.3 -0.3 to VDD+0.3 0 to +70 -55 to +150 1.0 50 Units V V V V C C W mA
ISSI
Notes 1 1 1 1 1 1 1 1
(R)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions (TA = 0C to 70C)
Symbol VDD VDDQ VIH VIL VoH VIL Parameter Supply Voltage Supply Voltage for Output Input High Voltage Input Low Voltage Output Logic High Voltage Output Logic Voltage Rating Min. 3.0 3.0 2.0 -1.0 2.4 -- Typ. 3.3 3.3 3.0 -- -- -- Max. 3.6 3.6 VDD + 0.3 0.8 -- Units V V V V V V Notes 1 1 1, 2 1, 3 IoH = IoL = mA mA
1. All voltages referenced to VSS and VSSQ. 2. VIH (max) = VDD + 2.3V for pulse width 3ns. 3. VIL (min) = VSS - 2.0V for pulse width 3ns.
Capacitance (TA = 25C, f = 1MHz, VDD = 3.3V 0.3V)
Symbol CI CO Parameter Input Capacitance (A0-A11, BA0, BA1, CS, RAS, CAS, WE, CKE, DQM) Input Capacitance (CK) Output Capacitance (DQ0 - DQ15) Min. 2.5 2.5 4.0 Typ 3.0 2.8 4.5 Max. 3.8 3.5 6.5 Units pF pF pF Notes
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IS42S16800A1
ISSI
Parameter Min. -1 -1 2.4 -- Max. +1 +1 -- 0.4 Units A A V V
(R)
DC Electrical Characteristics (TA = 0 to +70C, VDD = 3.3V 0.3V)
Symbol II(L) IO(L) VOH VOL Input Leakage Current, any input (0.0V VIN VDD), All Other Pins Not Under Test = 0V Output Leakage Current (DOUT is disabled, 0.0V VOUT VDDQ) Output Level (LVTTL) Output "H" Level Voltage (IOUT = -2.0mA) Output Level (LVTTL) Output "L" Level Voltage (IOUT = +2.0mA)
DC Output Load Circuit
3.3 V 1200 Output 50pF 870 VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA
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IS42S16800A1
dc
ISSI
Symbol Test Condition 1 bank operation tRC = tRC(min), tCK = min Active-Precharge command cycling without burst operation CKE VIL(max), tCK = min, CS = VIH(min) CKE VIL(max), tCK = Infinity, CS = VIH(min) CKE VIH(min), tCK = min, CS = VIH (min) CKE VIH(min), tCK = Infinity, CKE VIH(min), tCK = min, CS = VIH (min) CKE VIL(max), tCK = min, tCK = min, Read/ Write command cycling, Multiple banks active, gapless data, BL = 4 tCK = min, tRC = tRC(min) CBR command cycling CKE 0.2V 10 3 Speed (3.3V) -7 -75 Units Notes
(R)
Operating, Standby, and Refresh Currents
(TA = 0 to +70C)
Parameter
Operating Current
ICC1
5
85
mA
1, 2, 3
Precharge Standby Current in Power Down Mode
ICC2P ICC2PS ICC2N ICC2NS ICC3N ICC3P ICC4 ICC5 ICC6
2.5 2.5 5 9 0 9
2.5 2.5 45 9 50 9 120 190 3
mA mA mA mA mA mA mA mA mA
1 1 1, 5 1, 7 1, 5 1, 6 1, 3, 4 1 1
Precharge Standby Current in Non-Power Down Mode
No Operating Current (Active state: 4 bank) Operating Current (Burst Mode) Auto (CBR) Refresh Current Self Refresh Current
1. Currents given are valid for a single device. . 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min). 3. The specified values are obtained with the output open. 4. Input signals are changed once during tCK(min). 5. Input signals are changed once during three clock cycles. 6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). 7. Input signals are stable.
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IS42S16800A1
AC Characteristics (TA = 0 to +70C, VDD = 3.3V 0.3V)
ISSI
(R)
1. An initial pause of 200s, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and VIL (or between VIL and VIH) 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point 5. Load Circuit A: AC measurements assume tT = 1.0ns. 6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point 7. Load Circuit B: AC measurements assume tT = 1.2ns.
.
AC Characteristics Diagrams
tT Clock tSETUP tCKL tCKH VIH 1.4V VIL Output Vtt = 1.4V 50 Zo = 50 50pF
tHOLD 1.4V
AC Output Load Circuit (A)
Input
Output tAC tLZ Output 1.4V tOH
Zo = 50
50pF
AC Output Load Circuit (B)
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IS42S16800A1
Clock and Clock Enable Parameters
Symbol tCK3 tCK2 tAC3 (A) tAC2 (A) tAC3 (B) tAC2 (B) tCKH tCKL tCES tCEH tSB tT Parameter Clock Cycle Time, CAS Latency = 3 Clock Cycle Time, CAS Latency = 2 Clock Access Time, CAS Latency = 3 Clock Access Time, CAS Latency = 2 Clock Access Time, CAS Latency = 3 Clock Access Time, CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Clock Enable Set-up Time Clock Enable Hold Time Power down mode Entry Time Transition Time (Rise and Fall) 0 0.3 -7 Min. 7.0 7.5 -- -- -- -- 2 2 1.5 Max. 1000 1000 -- -- 5 5.4 -- -- -- -- 6 8 7.5 10 -- -- -- -- 2.5 2.5 1.5 0.8 0 0.5 -75 Min. Max. 1000 1000 -- -- 5.4 6 -- -- -- -- 7.5 10
ISSI
Units Notes ns ns ns ns ns ns ns ns ns ns ns ns 1 1 2 2
(R)
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A. 2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
Common Parameters
Symbol tCS tCH tAS tAH tRCD tRC tRAS tRP tRRD tCCD Parameter Command Setup Time Command Hold Time Address and Bank Select Set-up Time Address and Bank Select Hold Time RAS to CAS Delay Bank Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time CAS to CAS Delay Time -7 Min. 1.5 0.8 1.5 0.8 16 54 36 16 12 1 Max. -- -- -- -- -- -- 100K -- -- -- Min. 1.5 0.8 1.5 0.8 20 67.5 45 20 15 1 -75 Max. -- -- -- -- -- -- 100K -- -- -- Units ns ns ns ns ns ns ns ns ns CK 1 1 1 1 1 Notes
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
Symbol tRSC Parameter Mode Register Set Cycle Time -7 Min. 12 Max. -- Min. 15 -75 Max. -- Units ns
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IS42S16800A1
ISSI
Parameter -7 Min. -- 2.5 0 3 2 Max. -- -- -- 6 -- -75 Min. -- 2.7 0 3 2 Max. -- -- -- 7 -- Units Notes ns ns ns ns CK 3 1 2, 4
(R)
Read Cycle
Symbol
tOH tLZ tHZ tDQZ 1. 2. 3. 4.
Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
AC Output Load Circuit A. AC Output Load Circuit B. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).
Refresh Cycle
Symbol tREF tSREX Refresh Period Self Refresh Exit Time Parameter -7 Min. -- 1 Max. 64 -- -75 Min. -- 1 Max. 64 -- Units Notes ms CK 1
1. 4096 auto refresh cycles.
Write Cycle
Symbol tDS tDH tDPL tWR tDAL3 tDAL2 tDQW Data In Set-up Time Data In Hold Time Data input to Precharge Write Recovery Time Data In to Active Delay CAS Latency = 3 Data In to Active Delay CAS Latency = 2 DQM Write Mask Latency Parameter -7 Min. 1.5 0.8 12 12 5 4 0 Max. -- -- -- -- -- -- -- -75 Min. 1.5 0.8 15 15 5 4 0 Max. -- -- -- -- -- -- -- Units ns ns ns ns CK CK CK
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IS42S16800A1
Clock Frequency and Latency
Symbol fCK tCK tAA tRP tRCD tRC tRAS tDPL tDAL tRRD tCCD tWL tDQW tDQZ tCSL Clock Frequency Clock Cycle Time CAS Latency Precharge Time RAS to CAS Delay Bank Cycle Time Minimum Bank Active Time Data In to Precharge Data In to Active/Refresh Bank to Bank Delay Time CAS to CAS Delay Time Write Latency DQM Write Mask Latency DQM Data Disable Latency Clock Suspend Latency Parameter -7 143 7.0 3 3 3 9 6 2 5 2 1 0 0 2 1 -75 133 7.5 3 3 3 9 6 2 5 2 1 0 0 2 1 Units MHz ns CK CK CK CK CK CK CK CK CK CK CK CK CK
ISSI
(R)
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IS42S16800A1
40
\
(Burst length = 4, CAS latency = 2)
T0 T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
CK
tCKL tCS tCH tCEH tCK2
tCKH
CKE
tCES
CS
AC Parameters for Write Timing
RAS
CAS
WE
* BA1
tAH
RAx RBx RAy RAz RBy
A10
tAS
RAx CAx RBx CBx RAy CAy
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tRCD tDAL tRC
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3
N
A0-A9, A11
RAz
RBy
DQM
tDS
Ay0
tDPL tDH
Ay1 Ay2 Ay3
(c)
DQ
Hi-Z
tRP
tRRD
*BA0 = "L"
Bank2,3 = Idle
Activate Write with Activate Write with Command Auto Precharge Command Auto Precharge Bank 0 Command Bank 1 Command Bank 0 Bank 1
ISSI
tDPL and tDAL depend on clock cycle time and speed sort. See the Clock Frequency and Latency Table.
Activate Command Bank 0
Write Command Bank 0
Precharge Command Bank 0
Activate Command Bank 0
Activate Command Bank 1
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
AC Parameters for Read Timing (3/3/3)
Rev. 00B 05/01/06
(Burst length = 4, CAS latency = 3; tRCD, tRP = 3)
T0 T1 T10 T11 T13 T12 T2 T3 T4 T5 T6 T7 T8 T9
CK
tCK3
Begin Auto Precharge Bank 0 Begin Auto Precharge Bank 1
CKE
CS
RAS
CAS
WE
* BA1
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RAx RBx RAy RAx CAx RBx CBx RAy
A10
A0-A9, A11
tRRD tRAS
DQM
tRC tAC3 tOH
tRP
(c)
tRCD
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2
DQ
Hi-Z
* BA0 = "L"
Activate Command Bank 0
Bank2,3 = Idle
Read with Auto Precharge Command Bank 0
Activate Command Bank 1
Read with Auto Precharge Command Bank 1
Activate Command Bank 0
ISSI
(R)
41
IS42S16800A1
42
\
(Burst length = 2, CAS latency = 2; tRCD, tRP = 2)
T0 T1 T10 T11 T13 T12 T2 T3 T4 T5 T6 T7 T8 T9
CK
tCKH tCKL tCES tCH tCS
Begin Auto Precharge Bank 0 Begin Auto Precharge Bank 1
tCK2 tCEH
CKE
CS
RAS
AC Parameters for Read Timing (2/2/2)
CAS
WE
* BA1
tAH
RAx RBx RAy
A10
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tAS
RAx CAx RBx CBx
N
A0-A9, A11
RAy
tRRD tRAS(min) tAC2 tRCD tLZ
DQM
tRC tOH
tRP tRP tHZ
Ax0 Ax1 Bx0
(c)
Note: Must satisfy tRAS(min) For -260: extend tRCD1 clock
tHZ
Bx1
DQ
Hi-Z
* BA0 = "L"
Activate Command Bank 0
ISSI
Bank2,3 = Idle
Read with Auto Precharge Command Bank 0
Activate Command Bank 1
Read with Auto Precharge Command Bank 1
Activate Command Bank 0
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
AC Parameters for Read Timing (3/2/2)
Rev. 00B 05/01/06
(Burst length = 2, CAS latency = 3; tRCD, tRP = 2)
T0 T1 T10 T11 T13 T12 T2 T3 T4 T5 T6 T7 T8 T9
CK
tCKH tCKL tCES tCH tCEH tCS
Begin Auto Precharge Bank 0 Begin Auto Precharge Bank 1
tCK3
CKE
CS
RAS
CAS
WE
* BA1
tAH
RAx RBx RAy
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tAS
RAx CAx RBx CBx RAy
A10
N
A0-A9, A11
tRRD tRAS tRC
DQM
tRP tAC3 tOH tLZ
Ax0
(c)
Note: Must satisfy tRAS(min). Extended tRCD 1 clock. Not required for BL 4.
tRCD
tHZ
Ax1
tRP
Bx0
tHZ
Bx1
DQ
Hi-Z
* BA0=" L"
Activate Command Bank 0
ISSI
Bank2,3=Idle
Read with Activate Auto Precharge Command Command Bank 1 Bank 0
Read with Auto Precharge Command Bank 1
Activate Command Bank 0
(R)
43
IS42S16800A1
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\
(Burst length = 2, CAS latency = 3; tRCD, tRP = 3)
T1 T10 T11 T13 T14 T12 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
tCK3
Begin Auto Precharge Bank 0 Begin Auto Precharge Bank 1
CKE
tCEH
CS
RAS
AC Parameters for Read Timing (3/3/3)
CAS
WE
* BA1
A10
RBx
RAx
RAy
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CAx RBx CBx
N
A0-A9, A11
RAx
RAy
DQM
tRAS (mIn) tRC tAC3 tRCD
tRRD
tRP tOH tRP
(c)
DQ
Hi-Z
Ax0
Ax1
Bx0
Bx1
Bank 2,3=Idle
ISSI
*BA0=" L"
Activate Command Bank 0
Note: Must satisfy tRAS(min). Read with Extended tRCD not required Auto Precharge for BL4. Command Bank 0
Activate Command Bank 1
Read with Auto Precharge Command Bank 1
Activate Command Bank 0
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
Mode Register Set
Rev. 00B 05/01/06
(CAS latency = 2)
T0 T1 T10 T11 T13 T15 T18 T19 T20 T22 T14 T16 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
CK
tCK2 tRSC
CKE
CS
RAS
CAS
WE
BA0,BA1
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Address Key
A10,A11
N
A0-A9
DQM
(c)
Precharge Command All Banks Mode Register Set Command Any Command
DQ
Hi-Z
tRP
ISSI
(R)
45
IS42S16800A1
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\
T0 T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
CK
tCK Minimum of 8 Refresh Cycles are required 2 Clock min.
CKE
High level is required
CS
RAS
CAS
Power-On Sequence and Auto Refresh (CBR)
WE
BS
A10
Address Key
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tRP tRC
Precharge 1st Auto Refresh Command Command All Banks 8th Auto Refresh Command
N
A0-A9, A11
DQM
DQ
Hi-Z
Mode Register Set Command
Any Command
ISSI
Inputs must be stable for 200s
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
Clock Suspension / DQM During Burst Read
Rev. 00B 05/01/06
(Burst length = 8, CAS latency = 3; tRCD = 3)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
tCK3 tCEH
tCES
CKE
CS
RAS
CAS
WE
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RAx RAx CAx
* BA1
A10
N
A0-A9, A11
DQM
(c)
Ax0 Ax1 Ax2 Ax3 Ax4
tHZ
Ax6 Ax7
DQ
Hi-Z
* BA0=" L"
Read Command Bank 0
Bank2,3=Idle
Activate Command Bank 0
Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
ISSI
(R)
47
IS42S16800A1
48
\
(Burst length = 8, CAS latency = 3; tRCD = 3)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
tCK3
CKE
CS
RAS
CAS
Clock Suspension / DQM During Burst Write
WE
* BA1
A10
RAx
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RAx CAx DAx0 DAx1 DAx2 DAx3 DAx5
N
A0-A9, A11
DQM
DQ
Hi-Z
DAx6
DAx7
* BA0=" L"
Write Command Bank 0
ISSI
Bank2,3=Idle
Activate Command Bank 0 Clock Suspend 1 Cycle
Clock Suspend 2 Cycles
Clock Suspend 3 Cycles
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
Power Down Mode and Clock Suspend
Rev. 00B 05/01/06
(Burst length = 4, CAS latency = 2)
T0 T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
CK
tCES tCES tSB
VALID
tCES
tCK2
CKE
CS
RAS
CAS
WE
* BA1
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RAx RAx CAx
A10
A0 -A9, A11
DQM
DQ
Hi-Z
tSB
Ax0 Ax1 Ax2
tHZ
Ax3
(c)
Activate Command Bank 0 ACTIVE STANDBY NOP Read Command Bank 0
* BA0=" L"
Clock Suspension Start
Clock Suspension End
Bank2,3=Idle
Precharge Command Bank 0
PRECHARGE STANDBY NOP Any Command
ISSI
(R)
49
IS42S16800A1
50
\
(CAS latency = 2)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
Auto Refresh (CBR)
tCK2
CKE
CS
RAS
CAS
WE
BS
A10
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
tRP tRC tRC
Auto Refresh Command Auto Refresh Command
N
A0-A9, A11
DQM
(c)
DQ
Hi-Z
ISSI
Precharge Command All Banks
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
Self Refresh (Entry and Exit)
Rev. 00B 05/01/06
(Note: The CK signal must be reestablished prior to CKE returning high.)
T1 T2 T3 T4 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 Tm+9 Tm+10 Tm+11 Tm+12 Tm+13 Tm+14 Tm+15
T0
CK
tCES
tCES
CKE
CS
RAS
CAS
WE
BS
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
tSB
Self Refresh Entry Power Down Entry
A10
N
A0-A9, A11
DQM
(c)
DQ
Hi-Z
tSREX
Self Refresh Exit Power Down Exit
tRC
Any Command
All Banks must be idle
ISSI
(R)
51
IS42S16800A1
52
\
(Burst length = 8, CAS latency = 3; tRCD, tRP = 3)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
tCK3
CKE
High
CS
RAS
CAS
WE
* BA1
Random Row Read (Interleaving Banks) with Precharge
A10
RAx
RBx
RBy
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 (c)
CBx
CAx
N
A0-A9, A11
RAx
RBx
RBy
CBy
DQM
tRCD
tAC3
DQ
Bx0 Bx1
Hi-Z
Bx2
Bx3
Bx4
Bx5
Bx6
Ax0
Ax1
Ax4
Ax5
Ax6
Ax7
By0
ISSI
* BA0=" L"
Activate Command Bank 1
Read Command Bank 1
Activate Command Bank 0
Read Command Bank 0
Precharge Command Bank 1
Activate Command Bank 1
Read Command Bank 1
Precharge Command Bank 0
Bank2,3=Idle
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
Random Row Read (Interleaving Banks) with Auto-Precharge
Rev. 00B 05/01/06
C (Burst length = 8, AS latency = 3; tRCD, tRP = 3)
T0 T1 T10 T11 T13 T14 T15 T16 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9 T18
CK tCK3
Start Auto Precharge Bank 1 Start Auto Precharge Bank 0
CKE
High
CS
RAS
CAS
WE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
RAx RAx
* BA1
RBy
A10
RBx
N
A0-A9, A11
CBx
RAx RAx
RBx
CAx
RBy
CBy
DQM
tRCD
tAC3
(c)
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax4 Ax5 Ax6 Ax7 By0
DQ
Hi-Z
ISSI
* BA0=" L" Bank2,3=Idle
Activate Command Bank 1
Read with Auto Precharge Command Bank 1
Activate Command Bank 0
Read with Auto Precharge Command Bank 0
Activate Command Bank 1
Read with Auto Precharge Command Bank 1
(R)
53
IS42S16800A1
54
\
(Burst length = 8, CAS latency = 3; tRCD, tRP = 3)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
tCK3
CKE
High
CS
RAS
CAS
WE
* BA1
A10
RBx
RAx
RAy
Random Row Write (Interleaving Banks) with Auto-Precharge
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
CAX RBx CBx RAy
N
A0-A9, A11
RAx
CAy
DQM
tRCD
tDAL
tDAL
(c)
DQ
DAx0 DAx1 DAx4 DAx5
Hi-Z
DAx6
DAx7
DBx0
DBx1
DBx2
DBx3
DBx4
DBx5
DBx6
DBx7
DAy0
DAy1
DAy2
Activate Command Bank 0
Write with Auto Precharge Command Bank 0
Activate Command Bank 1
Write with Auto Precharge Command Bank 1
Activate Command Bank 0
* BA0=" L" Bank2,3=Idle
Write with Auto Precharge Command Bank 0
Number of clocks depends on clock cycle time and speed sort. See the Clock Frequency and Latency table. Bank may be reactivated at the completion of tDAL.
ISSI
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
Random Row Write (Interleaving Banks) with Precharge
Rev. 00B 05/01/06
(Burst length = 8,CAS latency = 3; tRCD, tRP = 3)
T1 T10 T11 T13 T20 T14 T15 T16 T18 T19 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9 T22
T0
CK
tCK3
CKE
High
CS
RAS
CAS
WE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 N
RBx RAy CAX RBx CBx RAy CAy
* BA1
A10
RAx
A0-A9, A11
RAx
DQM
tRCD
tRP
tDPL
(c)
DAx0 DAx1 DAx4 DAx5
DQ
Hi-Z
DAx6
DAx7
DBx0
DBx1
DBx2
DBx3
DBx4
DBx5
DBx6
DBx7
DAy0
DAy1
DAy2
Activate Command * BA0=" L" Bank 0 Bank2,3=Idle
Write Command Bank 0
Activate Command Bank 1
Write Command Bank 1
Precharge Command Bank 0
Activate Command Bank 0
Write Command Bank 0 Precharge Command Bank 1
ISSI
(R)
55
IS42S16800A1
56
\
(Burst length = 8, CAS latency = 3; tRCD, tRP = 3)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
Read / Write Cycle
tCK3
CKE
CS
RAS
CAS
WE
* BA1
A10
RAx
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
RAx CAx CAy Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 DAy4
N
A0-A9, A11
DQM
(c)
DQ
Read Command Bank 0
Hi-Z
ISSI
* BA0=" L" Bank2,3=Idle
Activate Command Bank0
The Read Data Write The Write Data is Masked with a Command is Masked with a Two Clock Bank 0 Zero Clock Latency Latency
Precharge Command Bank 0
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
Interleaved Column Read Cycle
Rev. 00B 05/01/06
(Burst length = 4, CAS latency = 3; tRCD, tRP = 3)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
tCK3
Start Auto Precharge Bank 0
CKE
CS
RAS
CAS
WE
* BA1
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
RBx CAx RBx CBx CBy CBz CAy
A10
RAx
N
A0-A9, A11
RAx
DQM
tRCD
tAC3
(c)
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 By1 Bz0 Bz1 Ay0 Ay1 Ay2 Ay3
DQ
Hi-Z
* BA0=" L"
Activate Command Bank 1
ISSI
Bank2,3=Idle
Activate Command Bank 0
Read Command Bank 0
Read Command Bank 1
Read Command Bank 1
Read with Read Precharge Command Auto Precharge Command Command Bank 1 Bank 1 Bank 0
(R)
57
IS42S16800A1
58
\
(Burst length = 4, CAS latency = 3; tRCD, tRP = 3)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
tCK3
CKE High
CS
Auto Precharge after Read Burst
RAS
CAS
WE
* BA1
A10
RBx
RAx
RBy
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 (c)
CAx CBx RBx CAy RBy
N
A0-A9, A11
RAx
CBy
DQM
Start Auto Precharge Bank 1
Start Auto Precharge Bank 0
Start Auto Precharge Bank 1
DQ
Ax0 Ax1
Hi-Z
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
ISSI
Activate Command * BA0=" L" Bank 0 Bank2,3=Idle Read Command Bank 0
Activate Command Bank 1
Read with Auto Precharge Command Bank 1
Read with Auto Precharge Command Bank 0
Activate Command Bank 1
Read with Auto Precharge Command Bank 1
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
Auto Precharge after Write Burst
Rev. 00B 05/01/06
(Burst length = 4, CAS latency = 2)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
tCK2
CKE
High
CS
RAS
CAS
WE
* BA1
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
RBx RBy RAz CAx RBx CBx CAy RBy CBy RAz CAz
A10
RAx
N
A0-A9, A11
tDAL
RAx
DQM
tDAL
tDAL
DQ
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2
Hi-Z
(c)
Write Command Bank 0 Write with Activate Command Auto Precharge Command Bank 1 Bank 1
DBx3
DAy0
DAy1
DAy2
DAy3
DBy0
DBy1
DBy2
DBy3
DAz0
DAz1
DAz2
DAz3
Activate Command Bank 0
Write with Write with Write with Activate Activate Auto Precharge Command Auto Precharge Command Auto Precharge Command Command Command Bank 1 Bank 0 Bank 0 Bank 0 Bank 1
* BA0=" L"
ISSI
Bank2,3=Idle
Number of clocks depends on clock cycle and speed sort. See the Clock Frequency and Latency table. Bank may be reactivated at the completion of tDAL.
(R)
59
IS42S16800A1
60
\
(Burst length = 4, CAS latency = 2)
T0 T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
CK
tCK2
CKE
High
CS
RAS
Burst Read and Single Write Operation
CAS
WE
* BA1
A10
RAv
A0-A9, A11
CAv CAw CAx
RAv
CAy
CAz
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Av0 Av1 Av2 Av3 DAw0 Ay0 Ay1 Av0 Av1 Av2 Av3
DAw0
N
LDQM
UDQM
(c)
DQ0 - DQ7
Hi-Z
Ay3
DAz0
DQ8 - DQ15
Hi-Z
DAx0
Ay0
Ay2
Ay3
DAz0
* BA0=" L"
Read Command Bank 0
ISSI
Lower Byte is masked Single Write Command Bank 0 Single Write Command Bank 0 Single Write Command Bank 0
Bank2,3=Idle
Activate Command Bank 0
Lower Byte Read is masked Command Upper Byte Bank 0 is masked
(R)
Rev. 00B 05/01/06
\
IS42S16800A1
CS Function (Only CS signal needs to be asserted at minimum rate)
Rev. 00B 05/01/06
(at 100MHz Burst Length = 4, CAS Latency = 3, tRCD, tRP = 3)
T1 T10 T11 T13 T14 T15 T16 T18 T19 T20 T22 T12 T17 T21 T2 T3 T4 T5 T6 T7 T8 T9
T0
CK
tCK3
CKE
CS
RAS
CAS
WE
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
RAx RAx CAx CAy
BA0,BA1
N
A10
A0-A9, A11
(c)
DQM Low
DQ
Activate Command Bank A Read Command Bank A
Hi-Z
tRCD
Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy2 DAy3
tDPL
Write Command Bank A
Precharge Command Bank A
ISSI
(R)
61
IS42S16800A1
ORDERING INFORMATION - VDD = 3.3V Commercial Range: 0C to 70C
Frequency 143 MHz Speed (ns) 7 Order Part No. IS42S16800A1-7TL Package 54-Pin TSOPII, Lead-free
ISSI
(R)
62
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. 00B 05/01/06
PACKAGING INFORMATION
Plastic TSOP 54-Pin, 86-Pin Package Code: T (Type II)
ISSI
N/2+1 E1 E
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
(R)
N
measured from the bottom of the package.
1 D
N/2
ZD
A
SEATING PLANE
e
b
A1
L
C
Symbol Ref. Std. No. Leads (N) A A1 A2 b C D E1 E e L L1 ZD
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 54 -- 0.047 0.002 0.006 -- -- 0.012 0.018 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 -- -- 0 8
Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 86 A A1 A2 b C D E1 E e L L1 ZD -- 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.12 0.21 22.02 22.42 10.16 BSC 11.56 11.96 0.50 BSC 0.40 0.60 0.80 REF 0.61 REF 0 8 -- 0.047 0.002 0.006 0.037 0.041 0.007 0.011 0.005 0.008 0.867 0.8827 0.400 BSC 0.455 0.471 0.020 BSC 0.016 0.024 0.031 REF 0.024 BSC 0 8
-- 1.20 0.05 0.15 -- -- 0.30 0.45 0.12 0.21 22.02 22.42 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 -- -- 0.71 REF 0 8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. C 01/28/02
1

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